ELEN500 Advanced Logic Design

January 7-March 11, 1999

Textbook

Grading

Course Schedule

7 January 99	Chapter 1 - Introduction VLSI design; optimization tradeoffs; motivation for synthesis; technology; complexity of algorithms Chapter 2 - A Quick Tour of Logic Synthesis
14 January 99	Chapter 3 Boolean Algebras Boolean Algebra basics, General Boolean Algebra for synthesis
21 January 99	Chapter 4 - Synthesis of Two-Level Circuits Design optimization, two level minimization; complexity of techniques for minimization
28 January 99	Chapter 4 - Synthesis of Two-Level Circuits (continued) Bounding the synthesis steps; multiple output minimization
4 February 99	HOUR EXAM - Chapters 1-4 Chapter 5 - Heuristic Minimization of Two-Level Circuits Techniques to improve synthesis tool performance
11 February 99	Chapter 7- Models of Sequential Systems Finite State Machines(FSM); state minimization; graph operations; equivalence checking; verification
18 February 99	Chapter 7 - Models of Sequential Systems (continued) Finish with FSMs Chapter 10 - Multilevel Logic Synthesis Extend two level concepts; heuristics added for multilevel logic
25 February 99	Chapter 12 - Automatic Test Generation Fault Models, excitation, sensitization, and redundancy
4 March 99	Chapter 13 - Technology Mapping
11 March 99	Related research topics.
18 March 99 7pm - 9pm	FINAL EXAM Chapters 1-5, 7, 10, 12, 13