ECEN 5223 LFSR and miniALU project

Spring 2008

Due Friday, 28 March 2008

ECEN 5223 Design Project Assignment 1, the LFSR applied to miniALU

This project is to apply BIST to a simple miniALU. All busses are to be numbered with 0 as the least significant bit. You are to create 2 different LFSRs:

a 20 bit LFSR with the Type 1 (external XOR) implementation of a pattern generator.
The polynomial for the pattern generator is x²⁰ + x³ + 1.
The input signals for the pattern generator LFSR are:
1 clock.
1 reset signal, sets all MSFFs to 1.
The output signals are:
20 bits of parallel output (1 from each state) for each of the 8 bit data inputs and 3 bits of control input
The input mapping is
- data x[7:0] to pat[19:12]
- data y[7:0] to pat[11:4]
- cin to pat[0]
- U to pat[1]
- L to pat[2]
- N to pat[3]

U = Uniop			single operand, input Y is ignored when U = 0
L = Logic operation			Logic operation do not use carry input, input cin ignored when L = 0
N = not			Complement input X when N = 1
Inputs to miniALU			Function or operation
U	L	N	Sum	Cout (each Cout bit for Logic operations)
0	0	0	X
0	0	1	not X
0	1	0	X plus cin (same as increment)
0	1	1	(not X) plus cin ( 2s complement if cin = 1 or 1s complement if cin=0)
1	0	0	X xor Y	X and Y
1	0	1	(not X) xor Y	(not X) and Y
1	1	0	X plus Y plus cin
1	1	1	(not X) plus Y plus cin

a 10 bit LFSR with the Type 1 (external XOR) implementation for a signature analyzer.
The polynomial for the signature analyzer is x¹⁰ + x⁷ + 1.
The input signals for the signature analyzer LFSR are:
1 clock.
8 bits of parallel input from the result bus (1 to each stage) .
1 reset signal, clears all MSFFs to 0.
The output signals are:
10 bits of parallel output (1 from each state).
The output from the miniALU into the signature analyzer mapping is
- result[7:0] to sigin[9:2]
- There is not a sigin[0]
- cout to sigin[1]

The design has a 100ns cycle time. The shift is on a postive edge of the clock.

The project is to be submitted via email in one attached file. There are a few specific details that must be true of your the top module.The top level module is proj1.The top level module must be defined with the following terminals:
module proj1(Reset, Signature, clk);
input Reset;
input clk;
output[9:0] Signature;

Note: this is an incompletely specified project assignment. As pre-lab work, be prepared to ask questions on Wednesday to complete the specification.

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