ECEN 4243

Syllabus for ECEN4243

Announcements

Lab and Homework Assignments

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Logon to take a quiz at WebCT ECEN 4243 page .

Course Schedule/Outline

Before you try to check your lab scores with the Automatic Grader, Read THIS OVERVIEW and read THIS login HELP page.
Automatic Grader Sometimes the Automatic grader has problems that are fixed by using the Alternate Automatic Grader on server 4.

We will be using the Cadence Design tools, which are licensed and installed at the Stillwater campus.
How to use the computer where the Simulator is running
Example decoder before synthesis.
pks-shell script for Example decoder synthesis.
Example decoder after synthesis.

The Standard Cell Library

Very Simple 1 bit ALU.
1 bit of a 3 port register.
Introduction to Stuck-At Logic Fault Models

External material

Verilog Tutorial: http://www.asic-world.com/verilog/index.html
Verilog Manual: http://www.see.ed.ac.uk/~gerard/Teach/Verilog/manual/index.html

Previous exams

ECEN 4243 Spring 2006 Exam 1 solution
ECEN 4243 Spring 2006 Exam 2 solution

ECEN 4243 Spring 2005 Exam 1 solution
ECEN 4243 Spring 2005 Exam 2 solution

ECEN 4243 Spring 2004 Exam 1 solution
ECEN 4243 Spring 2004 Exam 2 solution

ECEN 4243 Spring 2003 Exam 1 solution
ECEN 4243 Spring 2003 Exam 2 solution

ECEN 4243 Spring 2002 Exam 1 solution
ECEN 4243 Spring 2002 Exam 2 solution

[ECEN4243] [Announcements] [Schedule] [Syllabus] [Assignments]

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