ECEN 4243 Spring 2006

Computer Architecture

MWF 1:30-2:20

INSTRUCTOR: Dr. J. M. Acken
email: acken@okstate.edu Located in OSU-Tulsa
phone:(918)594-8122
office:North Hall rm 343
office hours:2:20-3:30 MW and by appointment

PREREQUISITES: ECEN 3213 and ECEN 3233 or equivalent knowledge of basic logic gate design. Previous experience in high level programming language and assembly language is highly recommended.

Stillwater TA: Jonathan Hildebrand email: jonathan.j.hildebrand@okstate.edu

office: Engineering South 103 in Lab
office hours: Tuesday and Thursday from 12:00-1:30 PM
or by appointment

Tulsa TA: see instructor email: TAecen4243

COURSE OBJECTIVES: To understand the design of a general purpose digital computer, including instruction set design, using a modern hardware description language(specifically Verilog).

BRIEF COURSE OUTLINE: See Detailed Course Outline

STYLE/MODE OF TEACHING: Informal lecture. Student questions are encouraged during lecture.

EXAMS AND MAJOR ASSIGNMENTS: There will be two one-hour exams during the term.
There will be a two-hour exam during finals week.

GRADING: 2 1-hr Exams (20% each)
Final Exam
Design Projects
Online Quizzes
Paper research/reports
40%
25%
15%
10%
10%

Grades will be determined as follows:
A
B
C
D
F
90% and above
80% - 89%
70% - 79%
60% - 69%
below 60%

Design project assignments will be graded automatically on the due date for each assignment. A late penalty of 10% per week will be assessed after the due date.

POLICY ON ATTENDANCE: Lecture attendance is optional. However, students are responsible for all material covered in lecture.

TEXT MATERIALS: Patterson and Hennessy Computer Organization and Design, Morgan Kaufman.
OTHER MATERIALS: All important information regarding the course will be on the class web site.
You should check the web site frequently for new announcements.
The following information is also available on the web site.
Design project assignments
Automatic grader
Sometimes the Automatic grader has problems that are fixed by using the Alternate Automatic Grader on server 4.

EXAMINATION POLICY: All exams are open book and open notes.
When taking exams, students should space themselves as far apart as possible.
No makeup exams or quizzes will be given. Students are expected to be present for all exams unless prior arrangements are made with the instructor.

POLICY ON DESIGN PROJECTS: Students are encouraged to discuss problems and solutions among themselves, but each student must do his/her own work. Copying designs (in part or in whole) will be considered academic dishonesty. It is the responsibility of each student to prevent his/her work from being copied. Both the student doing the copying and the student allowing the copying will be punished according to University procedures.
POLICY ON PAPER RESEARCH REPORTS: Each student will select different papers for their research reports. Students are encouraged to discuss papers among themselves, but each student must do his/her own work.

[ECEN4243] [Announcements] [Schedule] [Syllabus] [Assignments]

Feel free to email comments and suggestions to acken@okstate.edu

INSTRUCTOR:	Dr. J. M. Acken email: acken@okstate.edu	Located in OSU-Tulsa phone:(918)594-8122 office:North Hall rm 343 office hours:2:20-3:30 MW and by appointment
PREREQUISITES:	ECEN 3213 and ECEN 3233 or equivalent knowledge of basic logic gate design. Previous experience in high level programming language and assembly language is highly recommended.
Stillwater TA:	Jonathan Hildebrand	email: jonathan.j.hildebrand@okstate.edu
	office: Engineering South 103 in Lab office hours: Tuesday and Thursday from 12:00-1:30 PM or by appointment
Tulsa TA:	see instructor	email: TAecen4243
COURSE OBJECTIVES:	To understand the design of a general purpose digital computer, including instruction set design, using a modern hardware description language(specifically Verilog).
BRIEF COURSE OUTLINE:	See Detailed Course Outline
STYLE/MODE OF TEACHING:	Informal lecture. Student questions are encouraged during lecture.
EXAMS AND MAJOR ASSIGNMENTS:	There will be two one-hour exams during the term. There will be a two-hour exam during finals week.
GRADING:	2 1-hr Exams (20% each) Final Exam Design Projects Online Quizzes Paper research/reports	40% 25% 15% 10% 10%
	Grades will be determined as follows:
	A B C D F	90% and above 80% - 89% 70% - 79% 60% - 69% below 60%
	Design project assignments will be graded automatically on the due date for each assignment. A late penalty of 10% per week will be assessed after the due date.
POLICY ON ATTENDANCE:	Lecture attendance is optional. However, students are responsible for all material covered in lecture.
TEXT MATERIALS:	Patterson and Hennessy Computer Organization and Design, Morgan Kaufman.
OTHER MATERIALS:	All important information regarding the course will be on the class web site. You should check the web site frequently for new announcements. The following information is also available on the web site. Design project assignments Automatic grader Sometimes the Automatic grader has problems that are fixed by using the Alternate Automatic Grader on server 4.
EXAMINATION POLICY:	All exams are open book and open notes. When taking exams, students should space themselves as far apart as possible. No makeup exams or quizzes will be given. Students are expected to be present for all exams unless prior arrangements are made with the instructor.
POLICY ON DESIGN PROJECTS:	Students are encouraged to discuss problems and solutions among themselves, but each student must do his/her own work. Copying designs (in part or in whole) will be considered academic dishonesty. It is the responsibility of each student to prevent his/her work from being copied. Both the student doing the copying and the student allowing the copying will be punished according to University procedures.
POLICY ON PAPER RESEARCH REPORTS:	Each student will select different papers for their research reports. Students are encouraged to discuss papers among themselves, but each student must do his/her own work.