| Week | Date | Topic | Reading Assignment | Project |
| 1 | Jan9,11,13 | Basic review Introduction to HDL |
1.1-1.8 | |
| 2 | Jan 18,20 | Arithmetic Logic Unit (ALU) Design | 3.1-3.4 | |
| 3 | Jan23,25,27 | Combinational Logic Design with HDL | B.1-B.6 | |
| 4 | Jan30,Feb1,3 | Sequential Logic Design with HDL | B.7-B.11 | ALU |
| 5 | Feb6,8,10 | Simple Processor Architecture Instruction Decode |
5.1-5.5 | ALU |
| 6 | Feb13,15,17 | Control Unit Design | C.1-C.5 | ALU |
| 7 | Feb20 Feb22,24 |
Exam 1 Digital Testing | ||
| 8 | Feb27,Mar1,3 | Microprogrammed Control | 5.7 | ALU |
| 9 | Mar6,8,10 | Memory Organization and Management Select Research paper topic |
7.1 | ALU |
| break | Mar13,15,17 |
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| 10 | Mar20,22,24 | Cache Memory | 7.2-7.5 | Signature block and ALU |
| 11 | Mar27,29,31 | Exam 2 | Signature block | |
| 12 | Apr3,5,7 | Virtual Memory | 7.4 | ALU |
| 13 | Apr10,12,14 | Input/Output, Interrupts, DMA | 8.1-8.5 | ALU + Registers |
| 14 | Apr17,19,21 | Intel 8086 Family Research Paper selection closed |
ALU + Registers | |
| 15 | Apr24,26,28 | Real numbers IEEE standard representation |
6.1-6.3 | |
| May3[Wednesday] 2:00pm-3:50pm | Final Exam
Research Paper due | |||
Feel free to email comments and suggestions to
acken@okstate.edu
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