ECEN 4243 Spring 2006

Computer Architecture

Course Outline/Schedule

WeekDate TopicReading Assignment Project
1Jan9,11,13 Basic review
Introduction to HDL
1.1-1.8
2Jan 18,20 Arithmetic Logic Unit (ALU) Design 3.1-3.4
3Jan23,25,27 Combinational Logic Design with HDL B.1-B.6
4Jan30,Feb1,3 Sequential Logic Design with HDL B.7-B.11 ALU
5Feb6,8,10 Simple Processor Architecture
Instruction Decode
5.1-5.5 ALU
6Feb13,15,17 Control Unit Design C.1-C.5 ALU
7 Feb20
Feb22,24
Exam 1
Digital Testing
8Feb27,Mar1,3 Microprogrammed Control 5.7 ALU
9Mar6,8,10 Memory Organization and Management
Select Research paper topic
7.1 ALU
breakMar13,15,17
10Mar20,22,24 Cache Memory 7.2-7.5 Signature block and ALU
11Mar27,29,31 Exam 2 Signature block
12Apr3,5,7 Virtual Memory 7.4 ALU
13Apr10,12,14 Input/Output, Interrupts, DMA 8.1-8.5 ALU + Registers
14Apr17,19,21 Intel 8086 Family
Research Paper selection closed
ALU + Registers
15Apr24,26,28 Real numbers
IEEE standard representation
6.1-6.3
May3[Wednesday]
2:00pm-3:50pm
Final Exam
Research Paper due



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