ECEN 4243 ALU project

Spring 2006

Due Friday, 14 April 2006

ECEN 4243 Design Project Assignment 1 the ALU

Create a 32 bit ALU with 5 select lines. All busses are to be numbered with 0 as the least significant bit.

The input signals for the ALU are	The output signals are:
x and y are 32 bit busses. Cin is a one bit carry-in. clk is a one bit signal input to the Signature block. sel is a 5 bit function select bus.	res is a 32 bit result bus condition code bits: Cout is a one bit Carry-out. OVF is a one bit overflow. EQ is a one bit equal indicator. mch is a one bit match indicator. Z is a one bit zero result indicator.

Except where specifically set to a value in the following table, the Condition Code values are based upon these specifications: Z = 1 whenever all of the bits of SUM are 0; EQ = 1 whenever all of the bits of (X_i • oneOper) equals Y_i XOR complement; mch = 1 whenever all of the bits of Sin_i equals Yi; Cout = Cout of Bit 31; OVF = f(Cout, Result₃₁,sel).

sel	ALU function (i.e. value on result bus, Condition codes)
00000	y
00001	Stop signature, Res=LFSRcontents, Cout=0, mch=0
00010	Seed signature, Res=2, Cout=0, mch=1
00011	make 2's complement of y
00100	y XOR signature
00101	Cout=0; Res=32'hBA040105
01000	Step signature, Res=5, Cout==0
01010	x and y
01100	x or y
01111	x minus y(2's complement Arithmetic)
10000	restart signature, Res=3, Cout==0
10001	not y
10010	0
10100	x minus y(positive integers)
10101	x plus y(positive integers) OVF==Cout
11000	x XOR y
11011	x and not y
11101	x or not y
11110	x plus y(2's complement Arithmetic)

Note: all other select functions should generate all 0's on the results bus and a 1 on each condition code output. There are no don't care function select inputs. Fully decode each function select code into the appropriate control signals.

The project is to be submitted to the automatic grader. There are a few specific details that must be true of your uploaded files and the top module. The top level module is alu32 and the file containing the list of your module files is alu32.ver. The top level module must be defined with the following terminals:
module alu32(x,y, Cin, clk, sel, res, Cout, OVF, EQ, mch, Z);
input[31:0] x,y;
input[4:0] sel;
input Cin, clk;
output[31:0] res;
output Cout, OVF, EQ, mch, Z;

The signature block should have the following module definition:
module signature(Sig, clk, sel, MeasData);
input[31:0] MeasData;
input[4:0] sel;
input Cin, clk;
output[31:0] Sig;

When you upload the files there are two filenames to enter, your local filename (which can be anything) and the upload filename, which for the module files must end in .v and for the list of files must be alu32.ver.

[ECEN4243] [Announcements] [Schedule] [Syllabus] [Assignments]

Feel free to email comments and suggestions to acken@okstate.edu Today is And the time is ?

Last updated: