ECEN 4243 Signature
Due Tuesday, 4 April 2006
ECEN 4243 Design Project Assignment Signature Block
Load the
signature block verilog.
To run verilog for this example, include the new standard cell library:
verilog testbench.v design.v -v /x/cadence/osu_stdcells/flow/ami035/osu035_stdcells.v
Use the
testbench
to run verilog on the uploaded signature block.
The project is to be submitted to the automatic grader.
There are a few specific details that must be
true of your uploaded files and the top module.
The top level module is signature and the
file containing the list of your module files is
signature.ver.
The top level module must be defined with the
port terminals as in the signature block with the following module definition:
module signature(Sig, clk, sel, MeasData);
input[31:0] MeasData;
input[4:0] sel;
input clk;
output[31:0] Sig;
When you upload the files there are two filenames to enter,
your local filename (which can be anything) and the upload
filename, which for the module files must end in .v and for
the list of files must be Sig.ver.
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Feel free to email comments and suggestions to acken@okstate.edu
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