ECEN 4243 ALU with Registers and Instruction decode.

Spring 2005

Due 5pm Friday, 22 April 2005

ECEN 4243 Design Project Assignment 3 a very simple CPU

Use the ALU with registers that you designed for project 2, which was a 32 bit ALU with 5 select lines, and a register file with 8 addressable registers. What you are adding for this project is the instruction load and decode part of a simple control unit. This is a two cycle instruction, The first cycle is the fetch and decode, and the second cycle is the execute and memory access. The RW output should be set to a logic "1" when your processor is reading. The CPU should reset when input RESET is low. The PC register is set to 0 when reset is low. All busses are to be numbered with 0 as the least significant bit.

The MemData bus is the same as project 2, except, that it is input for instructions as well as data.
The input signals for the ALU with registers and Instruction decode are:
MemData which is a 32 bit bus.
RESET which is a 1 bit signal that resets the CPU when low.
clk is a one bit clock input.
Cin is tied to 0 for this project.
MemRead is a 1 bit memory read control signal that selects the MemData or the register file to be input on the y bus of the ALU.

The output signals are:
res is a 32 bit result bus
RW is an output that is a logic "1" when the CPU is reading data from the external data bus.
Address is a 32 bit address bus which is equal to PC (just a simple counter starting at 0, that is set to 0 whenever RESET is low) during the fetch cycle, it is equal to the last 15 bits of the instruction for a Branch, Load, or Store instruction, and set to z for other instructions.
Overflow is the high order Cout.

The ALU function selects are derived from the following instructions (these example instructions use particular addresses and registers but your design should be able to handle any 15 bit memory address or any 3 bit register address):

Instruction	Opcode	destination register address	source y register address	source x register address	immediate value (address for jmp, load, and store)
	8 bits	3 bits	3 bits	3 bits	15 bits
NOP	00000000	000	000	000	000000000000000
load R3, h00ff	01010100	011	000	000	000000011111111
store R5, h2AAA	01001100	000	101	000	010101010101010
and R5, R0, R7	00101000	101	000	111	000000000000000
or R1, R0, R7	00011000	001	000	111	000000000000000
xor R5, R0, R7	01011000	101	000	111	000000000000000
add R1, R0, R7	01100001	001	000	111	000000000000000
mov R1, R0	01000000	001	000	000	000000000000000
not R1, R0	00111111	001	000	000	000000000000000
bra h0987	11001100	000	000	000	000100110000111

The project is to be submitted to the automatic grader. There are a few specific details that must be true of your uploaded files and the top module. The top level module is alu32ireg and the file containing the list of your module files is alu32ireg.ver. The top level module must be defined with the following terminals:
module alu32ireg(MemData, MemRead, Address, RW, RESET, res, Overflow, clk);
input[31:0] MemData;
input MemRead, clk;
input RESET;
output[31:0] Address;
output[31:0] res;
output Overflow;
output RW;

When you upload the files there are two filenames to enter, your local filename (which can be anything) and the upload filename, which for the module files must end in .v and for the list of files must be alu32ireg.ver.

[ECEN4243] [Announcements] [Schedule] [Syllabus] [Assignments]

Feel free to email comments and suggestions to acken@okstate.edu