ECEN 4243 ALU with Registers project
Spring 2005
Due 11:47pm Wednesday, 23 March 2005
ECEN 4243 Design Project Assignment2 the ALU plus registers
Use the ALU you designed for project 1, which was a 32 bit ALU with 5
function select lines.
All busses are to be numbered with 0 as the least significant bit.
The registers are loaded via the ALU.
Specifically, the MemData bus is fed to the y input bus
of the ALU when MemRead is high.
Then the
register is loaded
by setting the function select to res = y (sel = 00000) and the
dest to the address of the target register.
Therefore, the value from memory is loaded into a register.
When MedRead is low, the contents of the register selected with srcy is
sent to the y input of the ALU.
The input signals for the ALU with registers are:
MemData which is a 32 bit bus.
Cin is a one bit carry in.
clk is a one bit clock input.
sel is a 5 bit function select bus.
dest, srcx, and srcy are 3 bit busses used to address the register file.
MemRead is a 1 bit memory read control signal that selects
the MemData or the register file to be input on the y bus of the ALU.
The output signals are:
res is a 32 bit result bus
Cout is a one bit Carry out.
Use the same ALU function
selects
as for project 1.
Note: all other select functions are reserved.
There are no don't care function select inputs.
Fully decode each function select code into the appropriate
control signals.
Register 0 is a special register that
always
has the value of 0.
Be sure to notice that the clock (clk) is an
explicit logic input to the module. The clock is used by the registers
to determine when values are stored. The result is stored on the rising edge
of the clock, for this assignment. The clock in the testbench will be 20 ns,
that is 10ns low and 10ns high.
The project is to be submitted to the automatic grader.
There are a few specific details that must be
true of your uploaded files and the top module.
The top level module is alu32wreg and the
file containing the list of your module files is
alu32wreg.ver.
The top level module must be defined with the
following terminals:
module alu32wreg(MemData, MemRead, dest, srcx, srcy, Cin, sel, res, Cout, clk);
input[31:0] MemData;
input MemRead, clk;
input[2:0] dest, srcx, srcy;
input[4:0] sel;
input Cin;
output[31:0] res;
output Cout;
When you upload the files there are two filenames to enter,
your local filename (which can be anything) and the upload
filename, which for the module files must end in .v and for
the list of files must be alu32wreg.ver.
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Feel free to email comments and suggestions to
acken@okstate.edu
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