ECEN 4243 ALU with Registers and Instruction decode.

Spring 2004

Due 5pm Friday, 30 April 2004

ECEN 4243 Design Project Assignment 3 a very simple CPU

Use the ALU with registers that you designed for project 2, which was a 32 bit ALU with 4 select lines, and a register file with 16 addressable registers. What you are adding for this project is the instruction load and decode part of a simple control unit. This is a two cycle instruction, The first cycle is the fetch and decode, and the second cycle is the execute and mem access. All busses are to be numbered with 0 as the least significant bit.

The MemData bus is the same as project 2, except, that is input for instructions as well as data. The input signals for the ALU with registers and Instruction decode are:
MemData which is a 32 bit bus.
clk is a one bit clock input.
Cin is tied to 0 for this project.
MemRead is a 1 bit memory read control signal that selects the MemData or the register file to be input on the y bus of the ALU.

The output signals are:
res is a 32 bit result bus
Address is a 32 bit address bus which is equal to PC (just a simple counter starting at 0) during the fetch cycle, it is equal to the last 12 bits of the instruction for a Branch, Load, or Store instruction, and set to z for other instructions.
Overflow is the high order Cout.

The ALU function selects are derived from the following instructions (these example instructions use particular addresses and registers but your design should be able to handle any 12 bit memory address or any 4 bit register address):

Instruction	Opcode	destination register address	source y register address	source x register address	immediate value (address for jmp, load, and store)
	8 bits	4 bits	4 bits	4 bits	12 bits
NOP	00000000	0000	0000	0000	000000000000
load R3, hff	01010100	0011	0000	0000	000011111111
store hAAA,R5	01001100	0000	0101	0000	101010101010
and R9, R0, R7	00101000	1001	0000	0111	000000000000
or R1, R0, R7	00011000	0001	0000	0111	000000000000
xor Rf, R0, R7	01011000	1111	0000	0111	000000000000
add R1, R0, R7	01100001	0001	0000	0111	000000000000
mov R1, R0	01000000	0001	0000	0000	000000000000
not R1, R0	00111111	0001	0000	0000	000000000000
bra h987	11001100	0000	0000	0000	100110000111

The project is to be submitted to the automatic grader. There are a few specific details that must be true of your uploaded files and the top module. The top level module is alu32ireg and the file containing the list of your module files is alu32ireg.ver. The top level module must be defined with the following terminals:
module alu32ireg(MemData, MemRead, res, Overflow, RW, clk);
input[31:0] MemData;
input MemRead, clk;
output[31:0] Address;
output[31:0] res;
output Overflow;
output RW;

When you upload the files there are two filenames to enter, your local filename (which can be anything) and the upload filename, which for the module files must end in .v and for the list of files must be alu32ireg.ver.

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Feel free to email comments and suggestions to acken@okstate.edu