ECEN 4243 Simple CPU
Spring 2003
Due 5pm Thursday, 1 May 2003
ECEN 4243 Design Project Assignment 4 a very simple CPU
This is an extra credit project
This uses the same design as project three.
Project 4 just tests more instructions.
Use the ALU with registers that you designed for project 2,
which was a 32 bit ALU with 4 select lines, and a register file with
8 addressable registers. What you are adding for this project is a
simple control unit and 3 special purpose registers.
This is a two cycle instruction.
The first cycle is the fetch and decode,
and the second cycle is the execute,
save results and memory access.
All busses are to be numbered with 0 as the least significant bit.
Contrary to my promise this project will not have timing checks!
The control unit state diagram is a simple two state machine
(fetch/decode cycle and execute/save results cycle).
The three special purpose registers are the
Program Counter,
the Instruction REGister, and the ADDress Register.
All digital computer systems and CPUs have three busses.
You will be implementing a bidirectional data bus,
an address bus
(output from the CPU), and part of a control bus(clk is input to CPU,
Reset is the power on reset signal that
sets the three control registers to 0,
and RW is the
output read/write signal from the CPU to memory,
and overflow is the output to indicate a system data exception.)
The Data bus is a bidirectional bus, that is input for instructions,
and might be input, output, or neither depending upon whether a load,
store or some other instruction is being executed. The CPU applies a z
(is disconnected from) the Databus when theCPU is not reading or writing
to memory. clk is the input clock.The low order Cin is tied to 0 for this
project. The output Address is a 32 bit address bus.
The Address bus is equal to PC (just a simple counter starting at 0)
during the fetch cycle, it is equal to the last 16 bits of the instruction
for a store instruction, and set to z for other instructions. The output signal
RW is the read/write control signal from CPU to memory. RW=1 when the CPU is
writing to memory, and RW=0 when the CPU is reading (or not using) the DATA bus.
The output signal Overflow is the high order Cout.
The ALU function selects are derived from the following instructions
(these example instructions use particular addresses
and registers
but your design should be able to handle any 16 bit memory address or
any 3 bit register addresses):
| Instruction |
Opcode | destination register address |
source y register address | source x register address |
immediate value (address for jmp, load, and store) |
|---|
| 7 bits | 3 bits | 3 bits | 3 bits | 16 bits |
| NOP | 0000000 | 000 | 000 | 000 | 0000000000000000 |
| load R3, hff | 1010100 | 011 | 000 | 000 | 0000000011111111 |
| store hAAAA,R5 | 1001100 | 000 | 101 | 000 | 1010101010101010 |
| and R1, R0, R7 | 0101000 | 001 | 000 | 111 | 0000000000000000 |
| or R1, R0, R7 | 0011000 | 001 | 000 | 111 | 0000000000000000 |
| xor R1, R0, R7 | 1011000 | 001 | 000 | 111 | 0000000000000000 |
| add R1, R0, R7 | 1100001 | 001 | 000 | 111 | 0000000000000000 |
| mov R1, R0 | 1000000 | 001 | 000 | 000 | 0000000000000000 |
| not R1, R0 | 0111111 | 001 | 000 | 000 | 0000000000000000 |
| jmp hAA | 1111110 | 000 | 000 | 000 | 0000000010101010 |
| Halt | 1111111 | 000 | 000 | 000 | 0000000000000000 |
The project is to be submitted to the automatic grader.
There are a few specific details that must be true of your uploaded files
and the top module. The top level module is simplecpu and the file
containing the list of your module files is simplecpu.ver.
The top level module must be defined with the following terminals:
module simplecpu(Data, Address, RW, overflow, Reset, clk);
input[31:0] Data;
output[31:0] Address;
output RW;
output overflow;
input clk, Reset;
When you upload the files there are two filenames to enter, your local filename
(which can be anything) and the upload filename, which for the module files must
end in .v and for the list of files must be simplecpu.ver.
Also, for the testbench in the autograder you need to
save and upload the floatbus module. The floatbus module is in
click here to get floatbus module and be sure
to add the file to your simplecpu.ver list of files.
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Feel free to email comments and suggestions to
acken@okstate.edu
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