ECEN 4243 Spring 2003 Exam 2 2 April 2003

Name________Solution__________

Read the instructions carefully before completing the exam. All answers must be shown on these pages – no attached pages will be graded. This exam is open book, open notes.

1. (15 points). The following instructions are executed in the order in the table. Fill in the following table with the register or memory location contents (in hexadecimal) after each instruction is executed. The instruction format is

Operation destination, sourceA, sourceB

or

Operation destination, source

or

Operation address

where destination or source can be registers or memory addresses.

	R1	R2	R5	mem h97	mem h98
Initial contents	h00	h29	h5A	h77	hFF
Mov R2, R5	h00	h5A	h5A	h77	hFF
Store h98, R2	h00	h5A	h5A	h77	h5A
Add R1, R1, R2	h5A	h5A	h5A	h77	h5A
LD R3, h97	h5A	h5A	h5A	h77	h5A
And R2, R5, R5	h5A	h5A	h5A	h77	h5A
Jmp 255	h5A	h5A	h5A	h77	h5A

2. (21 points). The following instructions are executed in the order in the table. Mark (with a Yes or No) which of the computer blocks is affected (i.e. changed or read) as the instruction is executed. Notice this does not include the fetch and decode steps.

	ALU	Register File	Main Mem	Program Counter	Instruction Register	Destination bus	Address bus
Mov R2, R5	Yes	Yes	No	No	No	Yes	No
NOP	No	No	No	No	No	No	No
Add R1, R1, R2	Yes	Yes	No	No	No	Yes	No
LD R3, h123	Yes	Yes	Yes	No	No	Yes	Yes
And R2, R2, R5	Yes	Yes	No	No	No	Yes	No
Store hFF, R1	Yes	Yes	Yes	No	No	Yes	Yes

3. (9 points) The following instructions are executed in the order in the table. Complete the following table showing the contents for the Program Counter during the fetch step, the Instruction Register during execution, and the Program counter after execution. These are 32 bit registers so show all 8 hex digits.

Instruction format reminder:

Op code 7 bits

destination reg address 3 bits

Src A register address 3 bit

Src B register address 3 bits

Value 16 bits

Use these binary Opcodes:

Add	1100001
Sub	1100000
LD	1010100
Store	1001100
And	0101000
Xor	1011000
Jmp	0111000
Halt	1111111
Nop	0000000
Mov	1000100

	Program counter during fetch	Instruction Register during execution	Program Counter after execution
Nop	h0000E099	h00000000	h0000E09A
Mov R2, R5	h0000E09A	h88A80000	h0000E09B
NOP	h0000E09B	h00000000	h0000E09C
Add R1, R1, R2	h0000E09C	hC24A0000	h0000E09D
LD R3, h123	h0000E09D	hA8c00123	h0000E09E
And R2, R2, R5	h0000E09E	h50950000	h0000E09F
Jmp hAA	h0000E09F	h70000AA	h000000AA

Consider the following logic circuit and the internally labeled nodes:

4 . (20 points) For the previous logic circuit fill out the following table:

X	Y	Cin	Sub	UniOp	Logic	ch1	ch0	Result	Cout	Pi	Gi	A	T
0	0	0	0	0	0	0	0	0	0	0	0	0	0
0	1	0	0	0	0	0	1	1	0	1	0	1	0
1	0	0	0	1	1	1	0	1	0	1	0	1	0
1	1	0	1	1	1	1	0	0	0	1	0	1	0
x	x	0	1	1	1	1	0	X	X	X	X	X	X
x	x	x	1	0	0	0	0	0	0	X	X	X	0
z