ECEN 4243 Spring 2002 Exam 2 5 April 2002

Name_______Solution_____

Read the instructions carefully before completing the exam. All answers must be shown on these pages – no attached pages will be graded. This exam is open book, open notes.

1. (20pts). The following instructions are executed in the order in the table. Fill in the following table with the register or memory location contents (in hexadecimal) after each instruction is executed.

	R1	R2	R5	h97	h123
Initial contents	h0	h2	h5	h7	hFF
Mov R7, R5	h0	h2	h5	h7	hFF
LD R6, h97	h0	h2	h5	h7	hFF
Add R1, R6, R2	h9	h2	h5	h7	hFF
LD R3, h123	h9	h2	h5	h7	hFF
Xor R5, R6, R3	h9	h2	hF8	h7	hFF
And R2, R2, R5	h9	h0	hF8	h7	hFF
Jmp 255	h9	h0	hF8	h7	hFF
Store R1, h123	h9	h0	hF8	h7	h9

2. (15pts). The following instructions are executed in the order in the table. Mark (with a Yes or No) which of the computer blocks is affected as the instruction is executed. Notice this does not include the fetch and decode steps.

	ALU	Register File	Main Memory	Program Counter	Instruction Register	Destination bus
Mov R7, R5	Yes	Yes	no	no	no	Yes
LD R6, h97	Yes	Yes	Yes	no	no	Yes
Add R1, R6, R2	Yes	Yes	no	no	no	Yes
LD R3, h123	Yes	Yes	Yes	no	no	Yes
Xor R5, R6, R3	Yes	Yes	no	no	no	Yes
And R2, R2, R5	Yes	Yes	no	no	no	Yes
Jmp hFF	no	no	no	Yes	Yes	no
Store R1, h123	Yes	Yes	Yes	no	no	Yes

3. (6pts) What are the three types of cache organization? __Direct Mapped_, __Set_Associative___, and _____Fully Associative________

4. (5pts) Which of those types of cache organization stores the full address with each word of data? ____Fully Associative__

5. (5pts) How many data words can be stored in the cache if the index portion of the address is 10 bits of a 32 bit address? _______1024__________

6. (10pts) The following instructions are executed in the order in the table. Complete the following table showing the contents for the Program Counter during the fetch step, the Instruction Register during execution, and the Program counter after execution. These are 32 bit registers so show all 8 hex digits.

Instruction format reminder:

Op code 7 bits

Destination reg address 3 bits

Src A register address 3 bit

Src B register address 3 bits

Value 16 bits

Use these binary Opcodes:

Add	1000000
Sub	1100000
LD	0010000
Store	0011000
And	1010000
Xor	1011000
Jmp	0000111
Halt	1111111
Nop	0000000
Mov	0010001

	Program counter during fetch	Instruction Register during execution	Program Counter after execution
Nop	h0000E000	h00000000	h0000E001
Mov R7, R5	h0000E001	h23E80000	h0000E002
LD R6, h97	h0000E002	h21800097	h0000E003
Add R1, R6, R2	h0000E003	h80720000	h0000E004
LD R3, h123	h0000E004	h20C00123	h0000E005
Xor R5, R6, R3	h0000E005	hB1730000	h0000E006
And R2, R2, R5	h0000E006	hA0950000	h0000E007
Jmp 255	h0000E007	h0E0000FF	h000000FF
Store R1, h123	h000000FF	h30080123	h00000100

7. (10pts) List all of the possible stuck-at faults for the following logic circuit:

D

Sub-stuck-at-0, Sub-stuck-at-1, X-stuck-at-0, X-stuck-at-1,

Y-stuck-at-0, Y-stuck-at-1, Cin-stuck-at-0, Cin-stuck-at-1,

A-stuck-at-0, A-stuck-at-1, B-stuck-at-0, B-stuck-at-1,

D-stuck-at-0, D-stuck-at-1, T-stuck-at-0, T-stuck-at-1,

Sum-stuck-at-0, Sum-stuck-at-1, Cout-stuck-at-0, Cout-stuck-at-1.

8. (10 points) For the previous logic circuit fill out the following table

Input Vector				Fault Free outputs			Node T-stuck-at-0 outputs		Check the box if the Stuck-at fault is detected for that vector
X	Y	Cin	Sub	Sum	Cout	Sum		Cout	A-s-a-0	A-s-a-1	T-s-a-0	Sum-s-a-0
0	0	0	0	0	0	0		0		ü
1	1	1	0	1	1	1		0		ü	ü	ü
0	0	0	1	1	0	1		0	ü			ü
0	0	1	1	0	1	0		1	ü
0	1	1	1	1	1	1		0		ü	ü	ü
1	1	1	1	0	1	0